The present invention relates to circuit simulators, and more particularly, to a method for extracting the inductance parameters for the various conductors in the metal layers of an integrated circuit.
Integrated circuits typically consist of a number of components fabricated in a semiconductor substrate that are connected by metal lines that are deposited in one or more layers over the semiconductor substrate. Each interconnect layer typically includes conductors that are parallel to one another or a conducting plane, such as a ground plane. The various interconnect layers and the semiconductor substrate are separated from one another by dielectric layers such as SiO2.
The delays and crosstalk introduced by the conductors in the metal layers can become bottlenecks, which limit overall circuit performance. Accordingly, the optimization of the on-chip interconnects is a goal of various simulation and optimization programs. To simulate and optimize on-chip interconnects, the parasitic parameters (resistance, capacitance and inductance) need to be extracted from the interconnect geometry. This extraction must be accurate, as a correlation with xe2x80x9cfinalxe2x80x9d verification engines is needed for design convergence. In addition, the extraction must also be efficient, because it may be performed dozens of times at the full-chip level and thousands of times on critical circuit paths.
To simplify the computations, prior art systems have ignored the inductive contributions and relied on the extraction of resistance and capacitance values. However, the increasingly wider and longer wire traces, faster clock frequencies and shorter rising times, utilized in modern circuits require that the inductance effects of on-chip interconnects must be included in the optimization calculations. However, no inductance extraction methodology, which is accurate and efficient for iterative simulation and optimization purposes, has been provided.
Unlike the estimation of parasitic capacitance, the mutual inductance between parallel conductors is not significantly diminished by the presence of additional conductors between the two conductors of interest. The capacitive effect, in contrast, is a xe2x80x9cshort-rangexe2x80x9d effect in the sense that for a block of parallel traces, only the mutual capacitance between adjacent traces are important, and the rest of the mutual capacitance can be ignored. Hence, the estimation of the inductive parameters is far more complicated than the estimation of the parasitic capacitances. In effect, mutual inductance must be computed for each pair of parallel conductors in the circuit that are not shielded from one another by a ground plane or the like.
Broadly, it is the object of the present invention to provide an improved method for extracting the parasitic inductive parameters for the metal interconnect layers of an integrated circuit.
It is a further object of the present invention to provide a method for extracting these parameters that is computationally efficient.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
The present invention is a method of operating a data processing system to estimate the inductance values associated with a first metal trace having a defined width, thickness, and length in an integrated circuit having a plurality of metal traces for carrying signals. In the present invention, the number and location of any ground planes adjacent to the first trace in the integrated circuit are first determined. A first current loop passing through the first trace that depends on the number and location of the ground planes, if any, is defined. The magnetic flux per unit area generated in the first current loop when a predetermined current passes through the first trace is then determined and used to estimate the self-inductance of the first trace. The flux depends on the width, thickness, and length of the trace, but is independent of the size and location of the other signal carrying traces in the integrated circuit. If the first trace overlies a first ground plane, the first current loop also passes through the first ground plane and depends on the distance between the first trace and the first ground plane. If the first trace also underlies a second ground plane, a second current loop is defined. The second current loop passes through the first conductor and the second ground plane. In this case, the determined flux also depends of the distance between the first trace and the second ground plane. The mutual inductance of the first trace and a second trace parallel thereto is determined by defining a current loop that passes through the first and second traces and determining the magnetic flux per unit area generated in the current loop when a predetermined current flows through the first trace. The determined flux depends on the distance between the first trace and the second trace, on the width, height, and length of the second trace, and on the distances to any ground planes, but is independent of the size and location of the other signal carrying traces in the integrated circuit. If the first trace and the second trace overlie a first ground plane, additional current loops passing through the ground plane and the first and second traces are also defined. Similarly, if the first and second trace also underlie a second ground plane, two additional current loops are defined, each passing through the second ground plane and one of the traces. The invention reduces the computational workload inherent in extracting inductance by substituting N two-trace problems for the general problem involving N parallel traces.